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HyperTransport 2.0: additional information

As we already reported in our news the day before yesterday HyperTransport 2 Standard.0 is accepted, details are ahead, the development of the new version of the standard has been successfully completed, it remains only to wait for its official announcement, which, according to eWeek, is scheduled for Monday.

Meanwhile, on the HyperTransport Technology Consortium website, there is still not a word about the upcoming announcement, and new details about the real capabilities of HyperTransport 2 are leaking onto the Web.0.

According to preliminary data, the new standard HyperTransport 2.0 describes three new bus speed levels: 2.0, 2.4 and 2.8 billion. operations per second at a clock speed from 1.0 GHz to 1.4 GHz, plus the maximum bus bandwidth, which increased in the 16-bit version to 22.4 Gb / s (12.8 Gb / s in the first implementation of the standard). For comparison: current implementations of HyperTransport 1.0 clocks up to 800 MHz. Tire width in version 2.0 remained unchanged; still 2-, 4-, 8-, 16-, or 32-bit widths are declared for a unidirectional bus.

Very little is known about the electrical changes in the tire characteristics, however, sources report that they are not significant; increased requirements for the sensitivity of the receiving part of the interface, the data exchange protocol is based on the “de-emphasis” technology. In addition to the increased interface performance, the new version 2 is also highlighted.0 the ability to support PCI Express host controllers by using similar interface registers and control methods, which will undoubtedly add flexibility to the new standard.

It is expected that the first products based on HyperTransport 2.0 will appear in the second half of 2021. We just have to wait for Monday and additional details about the new interface.

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